Kristen S. Davis

ZK3@zk3.net


 
Objective: A digital design or DSP internship for the summer of 2002.
 
Summary: 1 year of co-op experience in the Electronics arena, one year of experience in the Design Validation field.

Education:

MS Electrical Engineering.
    California Polytechnic State University, San Luis Obispo
    Major: Electrical Engineering                            Expected Graduation: June 2003

 
BS Electrical Engineering.
    California Polytechnic State University, San Luis Obispo
    Major: Electrical Engineering                            Graduated: September 2000
 

Related Course work:

    Digital Signal Processing                    Digital Filters
    Digital System Design                        Digital Integrated Circuits
    Digital Computer Subsystems            Stocastic Processes
    Computer Architecture                      CAD – VLSI Devices
    Digital Control Systems*                   Digital Image Processing*
    Fiber Optics*                                    *Classes in progress
 

Experience:

Motorola, Monterey                                    Sept. 2000 - Sept. 2001

Design Validation Engineer

Designed an automated voltage and temperature margining system using LabVIEW. Performed tests to verify Ethernet, USB, and PCI compliance and functionality.Installed windows based operating systems for stress and benchmarking tests.Create DVT plans for new compact PCI designsmaking sure new feature sets are verified.Accomplished by meeting with Design Engineer(s) prior to build.Attend Product Status meetings and update DVT schedules as necessary.Debug any found anomalie with new designs and feedback findings to EngineeringAttended and passes internal Motorola PCI classes.Installed windows based operating systems for stress and benchmarking tests.

Teradyne, Agoura Hills                            June – September 1999

Co-op Engineer

Designed a Mini Tester to test the electrical integrity of a new electrical interface design. Used Cadence: Concept for schematics and Allegro to create a Netlist for PCB layout. Used a DAQ to collect data and a GUI to control test options and display results.

IBM,San Jose                                            March – August 1998

Co-op Engineer

Used Cadence concept used to edit drawings for Engineering changes. Allegro software used to layout daughter boards for minor design changes. Troubleshot populated PCB’s for bad connections. Probed new ASIC’s to verify specifications. Created Lotus notes databases. Determined and documented Y2K compliance of office computers and test equipment.
 

Activities:

    Hunter/Jumper Equestrian Competition
    Triathlon Club – Pacific Grove ‘99-‘01 & Wildflower ’00 - '01 Triathlon finisher
    Cal Poly Wheelmen - Mountain & Road Bike Racing